The present invention is directed, in general, to a gated clock, and more specifically, to an xe2x80x9catomicxe2x80x9d gated clock cell.
A cell is a group of one or more circuit elements such as transistors, capacitors, and other basic circuit elements grouped to perform a function. Cell placement in semiconductor fabrication involves determining placement of particular cells on the surface of an integrated circuit, such as an application-specific integrated circuit (ASIC). Cell placement is one of the steps necessary for the fabrication of the ASIC. The ASIC has cells and connections between the cells, formed on a surface of a semiconductor substrate. The ASIC may include a large number of cells and require complex connections between the cells.
Due to the large number of components and the exacting details required by the fabrication process, a physical design of the ASIC is not practical without the aid of computers. As a result, most phases of physical design extensively use Computer Aided Design (CAD) tools, and many phases have already been partially or fully automated. Automation of the physical design process has increased the level of integration, reduced turn around time and enhanced chip performance.
However, the ASIC may have a large number, which can be tens of thousands, hundreds of thousands or even millions or more of small cells. Each cell represents a single logic element, such as a gate, or several logic elements interconnected in a standardized manner to perform a specific function. Cells are often arranged into cell libraries to facilitate their repeated use.
One goal of cell placement is to find a minimum area arrangement for the cells that allows completion of interconnections between the cells. Placement is typically done in two phases. In the first phase, an initial placement is created. In the second phase, the initial placement is evaluated and iterative improvements are made until the layout has minimum area and conforms to design specifications.
One such functionality that may be desired from the interactions and interconnections of the cells is that of forming a gated clock. A gated clock may generally be defined as a clock that generates a clock pulse that is substantially synchronous to a source clock signal when a gating signal is also asserted. The source clock signal is generally propagated throughout an ASIC in what is colloqially known as a xe2x80x9cclock tree.xe2x80x9d A gated clock may consist of a latch, perhaps an active low latch, and an AND gate.
In the ASIC world, a clock gating module is usually made up of two standard cells, such as an AND gate and a latch, which should ideally be placed very close to each other in the layout. A problem arose in the prior art when a cell placement tool placed clock gating modules far apart or sourced clock gating modules from different branches of the clock tree (a risk realized when clock gating modules are tied to different ASIC pins). Any resulting clock skew or propagation delay in the gating signal between the latch and the gate can cause a xe2x80x9crace conditionxe2x80x9d for the AND gate. An unwanted glitch can occur as a result of such race condition. The unwanted glitch may manifest as an additional undesired positive gated pulse, for instance. This problem is particularly annoying when there are a number of gated clocks in an ASIC design. To remedy this misplacement of the cells, the ASIC designer has been required manually to move the AND gate cell and the latch cell closer together.
For more information about cells, please see U.S. Pat. No. 6,243,849B1 to Singh, et al., which is hereby incorporated by reference in its entirety. Also for more information about clocks, please see U.S. Pat. No. 6,246,278B1 to Anderson, et al., which is hereby incorporated by reference in its entirety.
Accordingly, what is needed in the art is a gated clock that overcomes the limitations of the prior art. What is also needed is such gated clock that is employable as an atomic cell in a cell library.
To address the above-discussed deficiencies of the prior art, the present invention provides a clock gating cell and a method of manufacturing the same. In one embodiment, the clock gating cell includes: (1) gate signal and clock signal inputs configured to receive gate enable and clock input signals, respectively, and (2) a gated clock signal output configured to generate a gated clock signal that is a function of states of the gate enable and clock signals, the clock gating cell treated as an atomic entity in a cell library.
The present invention therefore introduces the concept of a unitary (xe2x80x9catomicxe2x80x9d) clock gating cell that is to be handled as an inseparable, indivisible entity in a cell library, thereby ensuring its proper operation. The present invention enjoys substantial utility in that it avoids race conditions that may otherwise occur when clock gating circuitry is divided between two or more cells.
Prior art clock gating circuits were not defined as a single cell and therefore risked being separated during compiling or being tied to different branches of a clock tree. Unfortunately, designers of such circuits were not motivated to recast such circuits as atomic entities, because separation did not always occur, and the risk was therefore unappreciated. Further, such separate circuits contained no motivation or suggestion that they could be recast as atomic entities.
In one embodiment of the present invention, internal circuitry of the clock gating cell comprises a latch configured to receive the gate enable and clock input signals and generate therefrom a latch enable signal. In an embodiment to be illustrated and described, the clock input signal is passed through a transparent low latch.
In one embodiment of the present invention, internal circuitry of the clock gating cell comprises combinatorial logic that generates the gated clock signal directly from the clock signal. In a more specific embodiment, the internal circuitry further comprises combinatorial logic that generates the gated clock signal from the latch enable and the clock input signal. In an embodiment to be illustrated and described, the combinatorial logic comprises an AND gate.
The foregoing has outlined, rather broadly, preferred and alternative features of the present invention so that those skilled in the art may better understand the detailed description of the invention that follows. Additional features of the invention will be described hereinafter that form the subject of the claims of the invention. Those skilled in the art should appreciate that they can readily use the disclosed conception and specific embodiment as a basis for designing or modifying other structures for carrying out the same purposes of the present invention. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the invention in its broadest form.